1. Field of the Invention
The present invention relates to semiconductor techniques, and more particularly to semiconductor devices and manufacturing method therefore.
2. Description of the Related Art
As part of the development of semiconductor techniques, the critical dimension (CD) of a contact has been greatly reduced especially for current logic devices.
As known by those skilled in the art, there are gate-last approaches and gate-first approaches for field-effect transistor manufacturing process.
Referring to FIG. 15, in the gate-last approach, a dielectric layer 1507 is formed on a substrate 1509, and a dummy gate is formed on the dielectric layer 1507. Preferably, a lightly doped region (LDD) implantation is carried out thereon, and then a spacer 1503 is formed on the sidewalls of the dummy gate 1501. After the formation of a gate structure with the dummy gate as described above, source region and drain region implantations are carried out, and a first dielectric interlayer 1505 is then formed and a chemical-mechanical polishing (CMP) process is performed, so as to substantially expose the upper surface of the dummy gate. The dummy gate is then removed. The dielectric layer 1507 can also be removed in some cases. Thereafter, a gate dielectric layer and a metal gate are formed, for example, by depositing a gate dielectric (in some instances, it may be a high-K dielectric) and then metal gate materials are deposited, followed by a CMP process, so as to form a metal gate 1501 where the dummy gate was previously formed. Then, the interlayer dielectric is re-coated so as to cover the gate. A contact hole 1521, 1523 is subsequently formed. And example of the resultant structure is shown in FIG. 15.
Similarly, the gate-first approach is similar to the conventional method of forming poly-silicon gate devices. A dielectric layer 1507 and gate 1501 are formed on a substrate 1509. Preferably, an LDD implantation is carried out and then a spacer 1503 is formed. After the formation of the gate structure as described above, source region and drain region implantations are carried out. A contact etch stop layer of silicon nitride and a first interlayer dielectric 1505 is formed covering the gate and then a contact hole 1521, 1523 is formed. The resultant structure, which is the same as in the gate-test approach is also as shown in FIG. 15.
Generally, covering the gate with the first interlayer dielectric is mainly to facilitate the formation of contact holes 1521 and 1523 to the gate and/or the active area, which contact holes are used for forming contact or wiring.
However, with the reduction in the size of contact critical dimension, the manufacturing process includes challenges, and open contact risk is also increased. For example, due to the reduction of contact critical dimension, a relatively thick resist may cause the etching of a contact hole (or, an opening) stop. Moreover, it is difficult to scale the contact CD down to a desired target value.
Further, for a contact hole shared by a contact to the active area and a contact to the gate, an open circuit problem may be encountered. Due to a thick resist or overlay variation, a poor connection between the active area and the gate can occur. Besides, the spacer may be etched, leading to an increased leakage from the top of the gate.
In addition, the aspect ratio is too high for a metal CVD (chemical vapour deposition) process to form the contact. As a result, it is difficult to properly control the resistance of the contact to be consistent with the designed or desired resistance. Also, the interlayer dielectric deposition has a small process window, which may result in voids.
Therefore, there exists a need to mitigate or address the above problems. To this end, a novel and creative method as proposed for manufacturing semiconductor devices, so as to mitigate or eliminate one or more problems existed in the prior art.